On June 9, 2026, a single research note lit a fuse under the hottest trade in AI hardware. Applied Optoelectronics fell around 17%, Coherent about 11%, Lumentum roughly 8%, Marvell near 8%, on the claim that two prized data-center technologies were slipping years behind schedule: co-packaged optics (CPO), which builds the optical transceiver into the network-switch chip package instead of plugging it in, and 800-volt direct-current power delivery, a higher-voltage way of feeding electricity to AI racks. The bearish call held that native 800V DC would slip to 2028 and beyond, and large-scale CPO to 2028–2029.[1][2] What actually happened is subtler than "the technology is delayed." A crowded trade priced for a 2027 ramp met a paywalled note read mostly through secondhand summaries, and the tape did the rest.
Why it matters now
The June 9 move was the second market shock in a week traced to the same research desk. On June 5, a note claiming NVIDIA would cut Vera Rubin rack memory from 55 TB to 28 TB sent Micron down 13%, its largest single-day drop since April 2025, on the very day Jensen Huang confirmed Micron, Samsung, and SK Hynix had all passed HBM4 certification for Vera Rubin.[3][4][5] Good news and bad news landed together, and the bad news won. That pattern is the story: names like Applied Optoelectronics had run up more than 400% year-to-date, pricing in a fast CPO adoption curve. When a slope estimate moved, valuations built on the old slope had nowhere to hide. The stakes are not whether these technologies arrive but the calendar on which revenue accrues to the companies staking their multiples on them.
The longer view
Over the next two to five years, the constraint on AI networking migrates from raw switch bandwidth to whether optics can be manufactured cheaply and reliably at the densities NVIDIA's roadmap demands. CPO's promise is real: NVIDIA's own figures cut ASIC-to-optics electrical loss from roughly 22 dB to about 4 dB and the optical path's power draw to as low as 9 watts, a claimed 3.5x efficiency gain.[6] But the same integration that delivers those gains concentrates manufacturing risk. Expect the value to spread across adjacent layers rather than pool in CPO alone: near-package optics (NPO), which mounts the optical engine on a pluggable board beside the chip, may accelerate as a near-term bridge; pluggable optics and the copper cables linking nearby racks retain their footing longer than bulls assumed.[1] On power, an interim 400V DC architecture is expected in volume from Q2 2026, with 800V reserved for the highest-draw platforms still being designed.[1][7]
The key insight
The core mechanism is yield compounding. CPO's economics live or die on a multiplication problem: NVIDIA's Spectrum-6 CPO switch integrates 32 optical engines into one package, and at an optimistic 95% attach yield per engine, system yield falls to roughly 19.4% because 0.95 multiplied by itself 32 times collapses. Reaching viable economics reportedly requires about 99.5% per-engine yield, and because the engines are soldered directly to the substrate, a single bad one cannot be reworked.[8] The old world plugged optics in, so a defective module was swapped at the port. The new world bakes them in, trading field-replaceable simplicity for lower power and higher density, and pushing the entire economic burden upstream onto manufacturing yield.
How it works
The binding constraint is signal reach at high speed. As switch ports climb toward multi-terabit rates, the electrical signal cannot travel far along a circuit board before it degrades, and pluggable optics sitting at the chassis face get harder to cool and to drive reliably.[9][10] CPO answers by moving the optical engine, the subassembly that converts electricity to light, right next to the switch chip so high-speed signaling stays off long board traces. NVIDIA's Spectrum-X Ethernet Photonics module packs 32 silicon-photonics engines, each running 3.2 Tbps across 16 transmit and 16 receive lanes.[11] What you gain: far less electrical loss and dramatically lower power.[6] What it costs: every one of those 32 engines must attach nearly perfectly, and none can be repaired after soldering.
Power delivery runs on a parallel logic. Feeding a rack at 800V instead of the current 48–54V standard eliminates conversion stages and cuts resistive losses, trimming facility-level power draw by about 5%.[7] That advantage only becomes decisive once a compute module exceeds roughly 15 kW.[7] The catch is platform dependence: baseline Rubin reportedly stays on a 50V solution and does not need 800V at all; the jump becomes essential only for higher-power Rubin Ultra and Feynman, whose specifications reportedly won't be finalized until late 2026.[7][8] So the near-term urgency the market had priced in was, on this reading, ahead of the hardware that would force the change.
Implications
Near term, the split between winners and laggards sharpens along the packaging axis. If scale-out CPO is genuinely yield-constrained, NPO and pluggable optics keep booking revenue while CPO-native suppliers wait, and copper cabling between adjacent racks stays relevant longer. That is why the same bearish desk that flagged the delay still named preferred bets across copper and active electrical cables, pluggable optics and their signal-processing chips, CPO test equipment, power backup, and board-level voltage regulation. On the power side, an interim 400V DC path expected in volume from Q2 2026 gives vendors like Delta Electronics and the broader power-semiconductor supply chain a nearer runway than the 800V headline suggests.[7]
Medium term, the roadmap does converge. As Rubin Ultra and Feynman push per-rack power past 600 kW and toward 1 MW, both native 800V DC and denser optics become unavoidable, likely around 2028–2029.[12][13] For engineers and operators, the skill premium shifts from designing around pluggable modules to managing integrated packages where a single defect strands an entire switch, and from 48V distribution toward high-voltage DC systems governed by newly expanded safety standards like UL 857's 14th edition, which raised DC coverage from 600V to 1000V.[14] The question for every supplier is not whether to build for this world but how much inventory and capex to commit before the slope is confirmed.
Tensions & open questions
Cause vs. coincidence. The double-digit drops on and after June 9 are verified.[15][2] The mechanism is not. One reading holds a paywalled note, read partially through summaries, mechanically de-risked a crowded trade; a stricter reading notes there is no direct evidence of overcrowded positioning, leaving causation as correlation.
The 19.4% yield math. One reading treats the 95%-per-engine, 99.5%-required calculation as the operative bottleneck.[8] A direct rebuttal argues the 0.95^32 figure is a pessimistic snapshot ignoring screening, binning, and redundancy, not a fundamental limit.[2] The primary text is inaccessible, so the numbers remain allegations.
The 800V calendar contradicts itself. One set of dates places native 800V at 2028+, tied to specs unfinished until late 2026.[16][17] Another cites Q3 2026 production readiness and Q1 2027 mass production at Delta.[18][19] An architecture cannot mass-produce before its specs are final, so at least one date set is mislabeling interim 400V racks or readiness milestones as native 800V.
Rebuttal signals vs. scale-up reality. NVIDIA's public CPO demonstration and "no delays" commentary may reflect early switch-to-switch or bridging volumes rather than GPU-attached scale-up CPO.[20] Several rebuttal specifics are not corroborated in the gathered evidence.
Talking points
- One research note knocked 8–17% off a batch of optical stocks in a day, but these names were up 150–400% for the year, so it was a crowded trade unwinding as much as a technology verdict.
- The killer number is yield: 32 optical engines at 95% each multiplies out to about 19% system yield, and you can't rework a soldered chip.
- It's the second shock in a week from the same desk, after a memory-cut note sent Micron down 13% the same day NVIDIA cleared it for HBM4.
- NVIDIA says baseline Rubin doesn't even need 800V power; the jump is reserved for Rubin Ultra and Feynman, whose specs aren't final until late 2026.
- The real debate isn't whether CPO happens, it's the slope, and that decides who wins between NPO, pluggables, and CPO-native plays.
The bottom line
- Core idea: CPO and 800V DC are constrained less by whether they work than by manufacturing yield and hardware timing, and a bearish note repriced both.
- Why it matters: Optical valuations built on a 2027 ramp cratered when the slope moved, and value is spreading to NPO, pluggables, and copper.
- What to watch: Whether per-engine CPO yields climb toward 99.5%, and whether native 800V shows up before Rubin Ultra's late-2026 specs.
Technical detail
The yield problem is compounded by an alleged margin issue. Beyond the attach-yield math, the note reportedly flagged a second-generation optical engine with onboard insertion loss exceeding 3.5 dB, exhausting the optical channel's error budget and underperforming the prior generation.[8] This is uncorroborated and sits awkwardly against NVIDIA's own specification citing electrical loss cut to about 4 dB as a headline feature, so it should be weighed as a claim, not a documented fault.[6] Watch how the industry resolves the gap between a 4 dB design target and a 3.5 dB reported defect.
On the roadmap axis, note the copper-to-optics gradient at rack scale. NVIDIA's GTC 2026 breakdown reportedly kept NVL72 and NVL144 fully copper, with optics appearing only at NVL1152 as CPO on the switch between racks.[21] That staging matters: it implies GPU-attached scale-up CPO, the volume-driving case, converges only when AWS, AMD, and Feynman projects align around 2029, while limited NVL576 units in 2027–2028 serve switch-to-switch interconnect at minimal volume.[22] The financial question is whether NPO persists as a durable parallel architecture or fades as a bridge once CPO yields mature.